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cy7c192 64 k 4 static ram with separate io cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05047 rev. *h revised june 1, 2011 64 k 4 static ram with separate io features high speed ? 15 ns cmos for optimum speed/power low active power ? 860 mw low standby power ? 55 mw ttl-compatible inputs and outputs automatic power down when deselected available in pb-free 28-pin molded soj package functional description the cy7c192 is a high performance cmos static ram organized as 65,536 4 bits with separate io. easy memory expansion is provided by active low chip enable (ce ) and tri-state drivers. it has an au tomatic power down feature that reduces power consumption by 75% when deselected. writing to the device is accomplished when the chip enable (ce ) and write enable (we ) inputs are both low. data on the four input pins (i 0 through i 3 ) is written into the memory location specified on the address pins (a 0 through a 15 ). reading the device is accomplished by taking the chip enable (ce ) low while the write enable (we ) remains high. under these conditions, the contents of the memory location specified on the address pins appears on the four data output pins. the output pins stay in high impedance state when write enable (we ) is low or chip enable (ce ) is high. a die coat ensures alpha immunity. array a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 10 a 11 a 13 a 12 a 14 a 15 column decoder row decoder sense amps power down we o 0 ce o 1 o 2 o 3 input buffer i 0 i 1 i 2 i 3 a 0 a 9 64k x 4 logic block diagram [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 2 of 12 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 4 switching characteristics ................................................ 5 switching waveforms ...................................................... 6 typical dc and ac characteristics ................................ 8 ordering information ........................................................ 9 ordering code definitions ........................................... 9 package diagram .............................................................. 9 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 12 worldwide sales and design s upport ......... .............. 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 3 of 12 pin configuration figure 1. 28-pin molded soj package gnd 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 o 3 o 2 o 1 o 0 a 0 ce 12 13 25 28 27 26 a 14 a 15 i 0 i 1 a 5 i 3 i 2 selection guide description -15 unit maximum access time 15 ns maximum operating current 145 ma maximum cmos standby current 10 ma [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 4 of 12 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ???????????????????????????????????? 65 c to +150 c ambient temperature with power applied ???????????????????????????????????????????????? 55 c to +125 c supply voltage to ground potential ????????????? ? 0.5 v to +7.0 v dc voltage applied to outputs in high z state [1] ??????????????????????????????????????? 0.5 v to v cc ?? 0.5 v dc input voltage [1] ????????????????????????????????? ? 0.5 v to v cc + 0.5 v output current into outputs (low) ............................ 20 ma static discharge voltage .......................................... > 900 v (per mil-std-883, method 3015) latch-up current .................................................. > 200 ma operating range range ambient temperature [ 2 ] v cc commercial 0 c to +70 c 5 v ? 10% electrical characteristics over the operating range parameter description test conditions -15 unit min max v oh output high voltage v cc = min, i oh = ? 4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v v il input low voltage [1] ? 0.5 0.8 v i ix input leakage current gnd < v i < v cc ? 5+5 ? a i oz output leakage current gnd < v o < v cc , output disabled ? 5+5 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ?145 ma i sb1 automatic ce power down current?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?30 ma i sb2 automatic ce power down current?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ?10 ma capacitance parameter description test conditions max unit c in [3] input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 8 pf c out [3] output capacitance 10 pf notes 1. minimum voltage is equal to ?2.0 v for pulse durations of less than 20 ns. 2. t a is the case temperature. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 5 of 12 figure 2. ac test loads and waveforms 3.0 v 5 v output r1 481 ?? r2 255 ?? 30 pf including jig and scope gnd 90% 10% 90% 10% < 3 ns < 3 ns 5 v output r1 481 ?? r2 255 ?? 5pf including jig and scope (a) (b) output 1.73 v equivalent to: th venin equivalent all input pulses 167 ?? over the operating range parameter [4] description -15 unit min max read cycle t rc read cycle time 15 ? ns t aa address to data valid ? 15 ns t oha output hold from address change 3 ? ns t ace ce low to data valid ? 15 ns t lzce ce low to low z [5] 3? ns t hzce ce high to high z [5, 6] ?7 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 15 ns write cycle [7] t wc write cycle time 15 ? ns t sce ce low to write end 10 ? ns t aw address setup to write end 10 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 9 ? ns t sd data setup to write end 9 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [5] 3? ns t hzwe we low to high z [5, 6] ?7 ns notes 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. at any temperature and voltage condition, t hzce is less than t lzce , t hzw\e is less than t lzwe for any given device. these para meters are guaranteed by design and not 100% tested. 6. t hzce and t hzwe are specified with c l = 5 pf as in part (b) of figure 2 . transition is measured ? 500 mv from steady-state voltage. 7. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 6 of 12 switching waveforms figure 3. read cycle no. 1 [8, 9] figure 4. read cycle no. 2 [8, 10] figure 5. write cycle no. 1 (we controlled) [11] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzce t pu data out high impedance impedance icc isb t hzce t pd ce high v cc supply current t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd ce we data in data out address notes 8. we is high for read cycle. 9. device is continuously selected, ce = v il . 10. address valid prior to or coincident with ce transition low. 11. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 7 of 12 figure 6. write cycle no. 2 (ce controlled) [12, 13] switching waveforms (continued) t wc data valid t sce t aw t sa t pwe t ha t hd t sd high impedance t hzwe address ce we data in data out notes 12. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. if ce goes high simultaneously with we high, the output remains in a high impedance state. [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 8 of 12 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 -55 25 125 ?55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( ? c) normalized supply current vs. ambient temperature ambient temperature( ? c) output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 sb sb i sb i cc i cc v cc =5.0v v cc =5.0v t a =25 ? c v cc =5.0v t a =25 ? c i sb t a =25 ? c 0.6 0.8 0 aa 1.3 1.2 v in =5.0v t a =25 ? c 1.4 v cc =5.0v v in =5.0v normalized i cc normalized i cc 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25 ? c v cc =5.0v t a =25 ? c v in =0.5v [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 9 of 12 ordering information speed (ns) ordering code package diagram package type operating range 15 CY7C192-15VXC 51-85031 28-pin molded soj (pb-free) commercial ordering code definitions temperature range: c = commercial package type: vx = 28-pin molded soj (pb-free) speed: 15 ns 92 = 256-kbit density with datawidth 4 bits 1 = fast asynchronous sram family technology code: c = cmos 7 = sram company id: cy = cypress c cy 1 - 15 vx 7 92 c package diagram figure 7. 28-pin (300-mil) soj (molded soj v21), 51-85031 51-85031 *d [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 10 of 12 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output soj small outline j-lead sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes ma milli amperes mm milli meter ms milli seconds mw milli watts ns nano seconds ? ohms % percent pf pico farad vvolts wwatts [+] feedback [+] feedback
cy7c192 document #: 38-05047 rev. *h page 11 of 12 document history page document title: cy7c192, 64 k 4 static ram with separate io document number: 38-05047 rev. ecn no. issue date orig. of change description of change ** 107149 09/10/01 szv change spec num ber from: 38-00076 to 38-05047 *a 359716 see ecn aju changed static discharge voltage limit in the maximum ratings section (page 2) from 2001v to 900v removed references to cy7c191 *b 419549 see ecn aju added pb-free parts to the ordering information table and replaced the package name column with package diagram *c 492500 see ecn nxr removed 20 ns and 25 ns speed bins changed the low active power from 220 mw to 55 mw changed the description of i ix from input load curr ent to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table removed 28-lead (300-mil) pdip package from product offering updated ordering information table *d 2104606 see ecn vkn/aesa re moved 12 ns speed bin *e 2956606 06/18/2010 kao removed inactive part from ordering information updated package diagram added sales, solutions, and legal information *f 3105329 12/09/2010 aju added ordering code definitions . *g 3217855 04/06/2011 pras added acronyms and units of measure . updated in new template. *h 3271782 06/01/2011 pras updated features . [+] feedback [+] feedback
document #: 38-05047 rev. *h revised june 1, 2011 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c192 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback [+] feedback

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